1. Field of the Invention
The present invention relates to transferring signals and, more particularly, to transferring signals between multiple clock timing domains.
2. Background Information
A common problem in digital communications is to transfer digital signals between multiple clock timing domains. It is not unusual to transmit digital signals between clock timing domains having the same underlying frequency clock, but different or varying phase with respect to each other. Typically, to solve this problem, synchronization or double synchronization may be introduced between the clock domains, such as by using a series of flip-flops or other hardware so that the timing of the digital signals transmitted is aligned. Therefore, the signals being transferred from one clock timing domain may be delayed by one or more clock cycles so that the signals may be synchronized with the clock signals in another clock timing domain, for example. Introducing such synchronization may cause undesirable and sometimes unpredictable delays in the communications path and, therefore, may result in performance degradation. Furthermore, as indicated previously, additional circuitry is typically required to delay the signals being transferred from one clock timing domain and to then synchronize those signals to another clock timing domain. Such additional circuitry will typically increase hardware complexity and cost. Such approaches also may create problems in the validation stage of a circuit design due to the use of circuit models to validate the design for different circuit models. These synchronizing circuit elements are typically modeled using different assumptions. If more than one circuit model is employed, as is frequently the case, then it becomes a difficult problem to validate the design. For example, different circuit models employ different assumptions regarding sample-and-hold times for digital signals to be acquired by digital circuitry without introducing metastability issues. The issue may also span different simulators. In some simulations, for example, no set-up or hold problems exist. In gate level simulations, however, these problems do exist. If inconsistencies occur in the validation performed by the different circuit models, then the design has not been successfully validated and sorting out the inconsistencies is an extremely complex problem. A need, therefore, exists for a technique of transferring signals between multiple clock timing domains that reduces or addresses these problems.